The credibility point is the most interesting part of this. In semiconductors, having a good design seems secondary to convincing customers that you'll still be around to support it years later. RISC-V lowers the barrier to building a CPU, but i'm not sure it lowers the trust barrier nearly as much.
By adding a bunch of IP blocks that do stuff the open ISA doesn't, like peripherals or multicore processing. It also helps if you can make it high throughout, low latency, or low power by adjusting some "knobs".
The HN article title suggests a contradiction where there isn't one. The instruction set is just the spec -- the high-level contract that the silicon must implement, with many important details like cycle counts per instruction left unspecified. It implies very little about how you would actually implement the inner workings, which could be done in an almost infinite number of different ways (including simulating them on some completely different architecture). Compare "How do you sell a calculator design when the rules of arithmetic are free?"
RISC-V is pretty unoptimisable though; the industry has had its fair share of pretty lackluster MIPS and MIPS-like clones in embedded, and they've been mainly high-volume low-cost "cheap and good enough" SoCs. To be competitive with ARM and x86 you really need higher code density and better, more complex instructions.
To be competitive with ARM and x86 they need a talented design team creating fast and wide cores on a modern node. (which I expect to take a decade at least)
For the vast majority of non-number-crunching code any theoretical difference between instruction sets vanishes in the noise of core design.
Is it? So there's no scope for different levels of pipelining, out-of-order execution with various numbers of execution units, branch prediction of various levels of sophistication, L1 cache of various amounts, multiplication and division implemented in various ways from slow but low chip area and power consumption to fast with high chip area or power consumption? Because those are all things that have major performance impact even on plain "RISC-style" x86-64 code.
I was pleasantly surprised it's a startup done by two of my conationals.
For the vast majority of non-number-crunching code any theoretical difference between instruction sets vanishes in the noise of core design.
Is it? So there's no scope for different levels of pipelining, out-of-order execution with various numbers of execution units, branch prediction of various levels of sophistication, L1 cache of various amounts, multiplication and division implemented in various ways from slow but low chip area and power consumption to fast with high chip area or power consumption? Because those are all things that have major performance impact even on plain "RISC-style" x86-64 code.